1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device with a digital circuit and an analog circuit on a common substrate, with a structure restricting cross-talk between the respective circuits via a semiconductor substrate, and a fabrication process therefor.
2. Description of the Prior Art
According to improvement of performance of a CMOS integrated circuit and a bipolar integrated circuit, silicon type integrated circuits have been used even in high operation frequency of GHz band. However, the silicon substrate has low insulation ability for its low resistance different from GaAs substrate typically used in the high operation frequency of GHz band. Therefore, there is relatively high possibility that an electrical signal generated in a certain element affects other elements via the substrate. Particularly, a signal generated in the digital circuit tends to flow into the analog circuit via the silicon substrate to cause degradation of analog characteristics in a semiconductor integrated circuit device, in which a digital circuit and an analog circuit are present on a common substrate. This phenomenon is referred to as substrate cross-talk which has been a serious problem in an integrated circuit, in which the digital circuit and the analog circuit are present on a common substrate. Therefore, how to restrict the cross-talk is a quite important factor to improve high frequency characteristics of the semiconductor integrated circuit device for expanding the applicable field in a high frequency range.
Therefore, there has been proposed an integrated circuit which can lower substrate cross-talk (Japanese Unexamined Patent Publication No. Hei 2-14549). FIG. 1 is a section showing a conventional semiconductor integrated circuit device, in which a digital circuit and an analog circuit are present on a common substrate. In this art, an analog circuit region 246 and a digital circuit region 248 are formed at the surface of a low concentration p-type silicon substrate 260. An oxide 272 is formed between the analog circuit region 246 and the digital circuit region 248 for isolating the analog circuit region 246 and the digital circuit region 248 from each other. Also, a high concentration p-type channel stopping high concentration region 265 is formed between the analog circuit region and the oxide 272. A grounding lead 267 connected to a grounding potential is formed on the channel stopper high concentration region 265. Similarly, a p-type channel stopping high concentration region 266 and a grounding lead 268 are formed between the digital circuit region 248 and the oxide 272. Then, an analog circuit transistor 270a, which is constructed with an n.sup.+ region 271a formed on the silicon substrate 260 and a base 272a, an emitter 273a, a collector 274a and an epitaxial layer 275a formed on the n.sup.+ region 271a, is formed in the analog circuit region 246. On the other hand, a digital circuit transistor 270b, which is constructed with an n.sup.+ region 271b formed on the silicon substrate 260 and a base 272b, an emitter 273b, a collector 274b and an epitaxial layer 275b formed on the n.sup.+ region 271b, is formed in the digital circuit region 248.
With this art, the oxide 272 having high resistance is present between the analog circuit region 246 and the digital circuit region 248. Therefore, a charge flowing between the analog circuit transistor 270a and the digital circuit transistor 270b can be reduced.
However, in the foregoing art, since a distance between the channel stopping high concentration regions 265 and 266 is narrow, resistance of the substrate 260 between the analog circuit transistor 270a and the digital circuit transistor 270b cannot be sufficiently high. Therefore, an effect of restricting cross-talk cannot be satisfactory. Cross-talk includes not only a charge flowing through the surface of the silicon substrate but also a charge flowing through the inside of the silicon substrate. In the foregoing art, while a charge flowing through the surface of the silicon substrate can be restricted, it may not be able to restrict a charge flowing through the inside of the silicon substrate.
The most efficient method in restricting cross-talk through the inside of the silicon substrate is to increase resistance of a silicon substrate per se. This can be achieved by using silicon having higher purity. A silicon substrate is produced by cutting a single crystalline silicon ingot. There are two methods, i.e. a CZ (Czochralski) method and an FZ (floating zone) method, for producing a single crystalline silicon ingot. The CZ method is a method to melt a silicon in a quartz melting pot, and a seed crystal of single crystalline silicon is soaked in the molten silicon and drawn up. This method is suitable for increasing the diameter of the ingot. However, since an impurity from the quartz melting pot may be admixed to lower resistance. Normally, specific resistance of a single crystalline silicon produced from the CZ method is not more than 50 (.OMEGA..multidot.cm). On the other hand, upon solidifying the molten silicon, the impurity can precipitated to make the specific resistance non-uniform.
On the other hand, in the FZ method, a single crystalline silicon ingot is produced by vertically setting a polycrystalline silicon bar with a seed crystal of single crystalline silicon seeded at the upper end with both ends fixed, locally heating the seeded portion for melting and shifting the melting zone downwardly from the upper end. In this method, a single crystalline silicon ingot having high purity and high resistance can be produced without possibility of admixing of an impurity. However, difficulty is encountered in increasing the diameter of the single crystalline silicon bar. Therefore, it is quite difficult to produce a large diameter silicon substrate at high specific resistance higher than or equal to 50 (.OMEGA..multidot.cm).
Therefore, another method for restricting cross-talk through the silicon substrate has been proposed (Japanese Unexamined Patent Publication No. Hei 4-251970). FIG. 2 is a section showing a conventional integrated circuit device, in which an analog circuit and a digital circuit are present on a common substrate. In this art, an n-type well region 312 for a digital circuit and an n-type well region 314 for an analog circuit are separately formed at the surface of a p-type silicon substrate 310. A p-channel MOS transistor and a p-type well region 315 are formed in the n-type well region 312. Also, an n-channel MOS transistor is formed in the p-type well region 315. Thus, a CMOS digital circuit is constructed with the p-channel MOS transistor and the n-channel MOS transistor. On the other hand, a p-channel MOS transistor and a p-type well region 318 are formed in the n-type well region 314. Also, an n-channel MOS transistor is formed in the p-type well region 318. Thus, a CMOS analog circuit is constructed with the p-channel MOS transistor and the n-channel MOS transistor. On the other hand, an n.sup.+ region 324 or a p.sup.+ region 326 are formed in the respective well regions 312, 314, 315 and 318. A power source potential V.sub.cc or a grounding potential GND is supplied through the n.sup.+ region 324 or the p.sup.+ region 326. Also, a grounding potential GND is supplied via a p.sup.+ region 328 to the p-type substrate 310.
With this art, the digital circuit region and the analog circuit region are separately formed in the n-type well region 312 and the n-type well region 314 respectively. The n-type well regions 312 and 314 are connected to a fixed potential, and isolated from each other by the substrate 310. Therefore, it can be successfully prevented to cause cross-talk between the digital circuit region and the analog circuit region.
However, when this structure is applied in a bipolar transistor circuit, operation characteristics of the circuit: can be degraded due to large parasitic capacitance. Therefore, the field of application of this technology is currently restricted only to a MOS transistor. Also, since the power source potential V.sub.cc or the grounding potential GND is applied to the respective well regions 312, 314, 315 and 318 via the n.sup.+ region 326 or the p.sup.+ region 328, excessive current to respective well regions is absorbed. However, a wiring for the power source and a wiring for the grounding potential are on the same plan as the other circuit wirings. Therefore, a wiring region for the power source and the grounding potential is necessary in addition to a wiring region for the other circuit wirings to cause increasing of the area of the integrated circuit.
On the other hand, there has been proposed a method for suppressing substrate cross-talk without increasing capacitance between a collector and a substrate even in a bipolar transistor (Japanese Unexamined Patent Publication No. Hei 3-148852). FIG. 3 is a section showing a conventional integrated circuit device, in which a digital circuit and an analog circuit are present on a common substrate. In this art, a silicon layer 406 is bonded on a silicon substrate 402 via an oxide layer 404 to form a SOI (Silicon On Insulator) structure. A portion where a digital circuit is to be formed and a portion where an analog circuit is to be formed are provided in the silicon layer 406 formed on the oxide layer 404. Also, an oxide layer 408 with a groove is formed between these portions. A conductive layer 410 is buried within the groove. The conductive layer 410 is connected to a grounding potential.
With this art, since the digital circuit and the analog circuit are separated by the oxide layer 408 as insulator, cross-talk can be suppressed. Also, since the inside of the groove between these circuits is fixed at a grounding potential, capacitive coupling between the digital circuit and the analog circuit can also be prevented successfully.
However, even in this structure, an electric signal may flow between the digital circuit and the analog circuit via thus silicon substrate 402 due to capacitive coupling via the oxide layer 404. The cross-talk thus caused cannot be prevented.